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it is in fact so far not possible to program Microchips controllers with CoDeSys. The reason is that for every single CPU platform there has to be a native code generator (compiler) developed and implemented into the tool. http://www.3s-software.com/index.shtml?en_CoDeSysSP_OEM for a full list).
This list will be extended, thus maybe Microchips CPUs will be supported in the future.
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when we develop the integrated compilers we optimize them for an optimum concerning the stability and use. Thus the existing ARM compiler supports all THUMB compatible derivatives as well as the THUMB2 compatible derivatives. Thus all ARM7/9/11 are supported as well as the Cortex M3/A8.
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Thanks ,As far I understand CoDeSys has stopped is runtime support for 8 bit cores from version3 and in 16 bit the Infineon coreC167 is only supported. But C167 comes under C166 family of Infineon and now Infineon has C166 S V2 . Does the CoDeSys compiler offer flexibility for this new core with the existing compilers
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yes.
As I explained we try to optimize the compilers in a way that they may be used in a most flexible way on different derivatives. This may cause some disadvantages concerning the instruction set. What I mean: in some cases limited instrcutions sets have to be used in order to maintain the compatibility, which will cause a little lower performance of the generated code. But in any case these compilers generate a much more powerful code than any interpreter system will do. And as they may be used on a wide range of derivatives of the same CPU platform the code is really reliable on all these platforms.
Thus all derivatives of the C167 series which support the original instruction set can be used for a new system.
In case you have more detailed questions please do not hesitate to contact me directly.
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I would like to know why CodeSys platform cannot be interfaced to Microchip controlleras . Can anyone guide me as to whether the same can be done
Regards
Rony
Hi,
it is in fact so far not possible to program Microchips controllers with CoDeSys. The reason is that for every single CPU platform there has to be a native code generator (compiler) developed and implemented into the tool.
http://www.3s-software.com/index.shtml?en_CoDeSysSP_OEM for a full list).
This list will be extended, thus maybe Microchips CPUs will be supported in the future.
Hi Wagner
Thanks for the update . As you mention that you support ARM core do you specifically support ARM CortexR4F core
Hi,
when we develop the integrated compilers we optimize them for an optimum concerning the stability and use. Thus the existing ARM compiler supports all THUMB compatible derivatives as well as the THUMB2 compatible derivatives. Thus all ARM7/9/11 are supported as well as the Cortex M3/A8.
Hi
Thanks ,As far I understand CoDeSys has stopped is runtime support for 8 bit cores from version3 and in 16 bit the Infineon coreC167 is only supported. But C167 comes under C166 family of Infineon and now Infineon has C166 S V2 . Does the CoDeSys compiler offer flexibility for this new core with the existing compilers
Hi,
yes.
As I explained we try to optimize the compilers in a way that they may be used in a most flexible way on different derivatives. This may cause some disadvantages concerning the instruction set. What I mean: in some cases limited instrcutions sets have to be used in order to maintain the compatibility, which will cause a little lower performance of the generated code. But in any case these compilers generate a much more powerful code than any interpreter system will do. And as they may be used on a wide range of derivatives of the same CPU platform the code is really reliable on all these platforms.
Thus all derivatives of the C167 series which support the original instruction set can be used for a new system.
In case you have more detailed questions please do not hesitate to contact me directly.