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Checking that option in the Static Analysis Light settings doesn't produce any warnings at compilation, even if I have 2 rungs writing to the same physical output.
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Should check even in same program. I tested it, and even in different programs it doesn't flag it as a problem.
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Anonymous
-
2016-12-12
Originally created by: scott_cunningham
Maybe I found what bbeal66 has trouble with.... If you define variables at specific memory locations (e.g. ```
Outs AT %QB0 : BYTE;
, then the static analysis reports multiple write error. If you define variables normally (e.g.
Outs : BYTE;
```) and then use the device I/O Mapping, static analysis does NOT report multiple write errors.
To me, this is a bug in the static analysis. I never use direct memory location definitions because I don't want to worry about changing all of those addresses when I simply switch the order of my EtherCAT devices!
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Checking that option in the Static Analysis Light settings doesn't produce any warnings at compilation, even if I have 2 rungs writing to the same physical output.
are the two rungs on the same prg?
if so you are just overwriting the last rung in the program as it goes through the prg sequentially.
the setting only applies if you are writing to the same output from multiple prg's I believe
Should check even in same program. I tested it, and even in different programs it doesn't flag it as a problem.
Originally created by: scott_cunningham
Maybe I found what bbeal66 has trouble with.... If you define variables at specific memory locations (e.g. ```
Outs AT %QB0 : BYTE;
, then the static analysis reports multiple write error. If you define variables normally (e.g.Outs : BYTE;
```) and then use the device I/O Mapping, static analysis does NOT report multiple write errors.
To me, this is a bug in the static analysis. I never use direct memory location definitions because I don't want to worry about changing all of those addresses when I simply switch the order of my EtherCAT devices!